Non-volatile memory is widely used in portable electronic devices (e.g., smart phones, personal digital assistants, tablet and notebook computers, digital cameras, digital audio players, etc.). Non-volatile memory retains its stored information even in the absence of power. It is also electrically erasable and reprogrammable, light-weight and durable, and requires no moving parts. All of these attributes lend well for use in portable electronic devices.
To satisfy increasing demand for higher-capacity flash memory while keeping manufacturing costs low, flash memory manufacturers have resorted to process scaling techniques in which the memory cells that make up the flash memory—known as “floating gate transistors”—are fabricated with smaller dimensions. By scaling down (i.e., “shrinking”) the individual floating gate transistors, higher capacity flash memories can be produced. Over the years, process scaling has proved to be remarkably successful, reducing the minimum feature size of floating gate transistors from around 1 micron (1,000 nanometers) in the early 1990s to around 25 nanometers today. However, the ability to scale down further is impeded by diffraction limits of the photolithography processes used in fabricating the floating gate transistors and by short channel effects and memory retention problems that arise when floating gate transistors are scaled down to nanometer dimensions.
To overcome these limitations, various alternative non-volatile memory technologies have been proposed. Some of these alternative non-volatile memory technologies have shown great promise. However, challenges to manufacturing the memory cells in a high-density array remain. The present invention addresses and provides solutions to these challenges.